General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A) Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B) Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev Basics of the CDC7005 Hold Function General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)