Pulse Frequency Modulation in DC-DC: PFM vs PWM

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This page covers PFM in DC-DC power supplies (not communication PPM/PDM/PAM). See FAQ.

What is Pulse Frequency Modulation (PFM) in DC-DC?

Pulse Frequency Modulation (PFM) is a light-load power-saving control mode in DC-DC converters that keeps the on-time nearly constant while reducing the switching frequency as load current drops. It is widely used in buck/boost/buck-boost regulators and PMICs to extend battery life.

Why it matters

Iq / light-load efficiency: lowers switching losses to stretch standby battery life.
Ripple pattern: variable-frequency pulse trains change ΔV_out characteristics.
EMI predictability: frequency wanders vs. fixed-frequency PWM; compliance strategy differs.
Audible-noise risk: when effective frequency dips below ~20 kHz.
ADC/RF sensitivity: jittered energy can couple into precision measurements or audio/RF paths.
PFM↔PWM transitions: entry/exit thresholds and transients must be considered in design.

How it works

In PFM, the regulator delivers bursts with a nearly constant on-time; the spacing between bursts increases at light load and decreases as load rises. By contrast, PWM keeps a fixed switching frequency and varies duty cycle. Many vendors name PFM as power-save / eco-mode / pulse-skipping.

PFM waveforms in DC-DC converters: constant on-time with variable pulse spacing; contrasted with fixed-frequency PWM — PFM (variable spacing) vs. PWM (fixed frequency, variable duty).

Where you meet it

You will encounter PFM in buck, boost, buck-boost regulators and PMICs as Auto-PFM↔PWM. Many devices expose a MODE/PS pin or register to force PWM when ripple/EMI or audible noise is critical.

Not sure about your load threshold? Jump to the Engineer’s Checklist.

PFM vs PWM: Quick Decision Table for DC-DC Converters

PFM (pulse frequency modulation) saves power at light load by lowering switching frequency, while keeping on-time nearly constant. PWM holds a fixed frequency and varies duty cycle for predictable ripple and EMI. Neither is “better” in all cases—your choice depends on I_q, ripple/EMI/noise, and transient behavior.

PFM vs PWM trade-offs across key design dimensions
Mode	I_q (light load)	f_sw stability	ΔV_out (ripple)	EMI / audible	Transients / switching	Typical use	Need MODE?
PFM (Auto-PFM)	Very low (µA-level possible)	Variable / pulse-skipping	Irregular; may add low-freq content	Spectrum spreads; risk <20 kHz noise	Mind PFM↔PWM entry/exit thresholds	Battery/IoT, standby-first designs	Yes—prefer parts that can force PWM
PWM (Forced-PWM)	Higher (fixed switching losses)	Fixed; SYNC-friendly	Predictable; easier to filter	Controlled EMI; add spread-spectrum if needed	Consistent response; simpler loop tuning	Audio/RF/precision ADC; EMI-critical nodes	MODE or register to force PWM is required

Battery life / ultra-low I_q
Choose Auto-PFM for wearables & low-duty IoT.

Fixed-freq, low ripple/noise
Prefer Forced-PWM for audio/RF/precision ADC.

Automotive / industrial
Use switchable modes + spread-spectrum for EMI budgets.

PFM vs PWM waveforms and trade-offs in DC-DC converters — PFM (variable spacing) vs PWM (fixed frequency; variable duty).

Need forcing conditions and thresholds? Jump to Section 3 (MODE / Forced-PWM). Want ripple/noise fixes? See Section 4.

PFM in Buck/Boost & MODE / Forced-PWM

After choosing between PFM and PWM, real designs hinge on entry/exit thresholds and how cleanly the converter transitions from bursty PFM to continuous PWM. In noise-sensitive nodes (audio/RF/precision ADC), you often force PWM via a MODE/PS pin or register.

Entry/Exit thresholds & transition behavior

Define two practical currents in the datasheet:

I_PWM→PFM (entry): as load falls, the regulator enters PFM below this current.
I_PFM→PWM (exit): as load rises, it leaves PFM and resumes continuous PWM above this current (often with hysteresis).

Near the threshold, expect the pulse spacing to compress; transitions can induce V_out dip/overshoot or sweep into the audible band. Keep sensitive rails above I_PFM→PWM or force PWM.

Design tip (preload): If you must avoid PFM on a sensitive rail, add a small preload to hold the load above the exit threshold. Use R_preload = V_out / I_preload, choosing I_preload ≳ I_PFM→PWM while balancing standby loss.

MODE / register control (Forced-PWM)

Typical logic is MODE = High → Forced-PWM, MODE = Low → Auto-PFM (some parts invert—always check the datasheet). Use Forced-PWM for audio/RF/precision ADC paths or any fixed-frequency EMI budget. Retain Auto-PFM on battery-critical branches for maximum efficiency.

MODE / Power-save naming & behavior (examples; see Section 9 for full picks)
Vendor / Series	Naming	MODE High	MODE Low	Notes
TI — TPS62840 / TPS62122	MODE / Power-save	Forced-PWM	Auto-PFM	Low I_q; some support spread-spectrum/SYNC
TI — TPS63070	Power-save / FPWM	Forced-PWM (buck-boost)	Auto-PFM (eco)	Buck-boost with eco-mode
ST — L6981 / ST1PS01	Low-power / FPWM	Forced-PWM	PFM / pulse-skipping	Fixed-freq options; AEC-Q variants exist
NXP — PCA9420 (PMIC)	Power-save	Forced-PWM (per rail via register)	Auto-PFM (per rail)	Multi-rail PMIC, register-controlled
Renesas — ISL91127/91126	Auto-PFM / PWM	Forced-PWM (mode pin/reg)	Auto-PFM buck-boost	Good for mid-power buck-boost rails
onsemi — NCP1529/1521	Power-save / FPWM	Forced-PWM	PFM (skip)	Compact bucks; mobile-focused
Microchip — MCP1640	PFM/PWM auto	Forced-PWM (variants)	Auto-PFM (boost)	Simple boost; great for coin-cell/AA

Stability & transient control around mode switching

Preload: hold the rail above I_PFM→PWM to avoid bursty operation on sensitive nodes.
Compensation / phase margin: validate margin near the exit point; retune if dip/overshoot appears.
Output capacitance & ESR: modest ESR helps tame spikes; consider extra C or an RC snubber.
Inductor value & ripple current: avoid saturation or sub-harmonics in the transition zone.
Synchronization: for ADCs, sync sampling to PWM or add anti-alias RC if PFM is unavoidable.

Auto-PFM to PWM transition threshold and behavior in DC-DC converters — As load crosses the exit threshold, PFM bursts compress into continuous PWM (often with hysteresis).

IC examples (cross-brand families)

TI: TPS62840 / TPS62122 (Buck), TPS63070 (Buck-Boost)
ST: L6981, ST1PS01 (Low-power mode + Forced-PWM)
NXP: PCA9420 (PMIC, per-rail power-save)
Renesas: ISL91127 / ISL91126 (Buck-Boost, Auto-PFM/PWM)
onsemi: NCP1529 / NCP1521 (Buck)
Microchip: MCP1640 (Boost, auto switching)
Melexis: Sensor/driver focused; pair with above regulators

Full parameters (MODE, I_q, f_sw, spread-spectrum/SYNC, AEC-Q) appear in Section 9.

Need ripple/EMI/audible fixes? See Section 4. Ready for cross-brand shortlists? Jump to Section 9 or Submit your BOM.

Ripple / EMI / Audible Noise — Problems → Actions

PFM spreads energy over variable frequency and saves power at light load, but can raise low-frequency ripple, EMI unpredictability, and audible noise. PWM holds fixed frequency for predictable filtering and compliance. Use the checklists below to diagnose symptoms and apply concrete fixes—then choose suitable MODE/Forced-PWM and IC options.

A) Audible noise < 20 kHz

Symptoms

Whine/chirp at light or no load; brief squeal on load steps.

Causes

PFM frequency sweeping into the audible band.
Magnetics mechanical resonance; MLCC piezoelectric effect.
SW node ringing/undershoot exciting acoustics.

Quick fixes

Force PWM (MODE/reg); or raise/lock f_sw.
Enable spread-spectrum or SYNC to avoid audible region.
Add a small preload to keep load above PFM exit threshold (see Section 3).
Swap to low-noise magnetics; parallel polymer/tantalum with MLCC; consider potting.
Add an RC snubber at SW (validate thermal loss).

IC hook

Prefer regulators with Forced-PWM, Spread-Spectrum, and SYNC support; clear PFM↔PWM thresholds.

Measurement

Sound level meter / mic + scope FFT; test at light-load and during load steps.

Layout / Parts

Minimize hot loop area (VIN-HSFET-SW-input cap-GND).
Limit SW copper splash; mechanically secure inductor; avoid MLCC stress.

B) Ripple / ADC / RF integrity

Symptoms

Irregular output ripple; ADC jitter/elevated noise floor; RF adjacent-channel issues.

Causes

PFM pulse-spacing jitter introduces low-frequency components.
SW ringing coupling into sensitive traces/grounds.
Sampling beating with switching frequency.

Quick fixes

Force PWM; synchronize ADC sampling to PWM; or move sampling away from harmonics.
Add RC preload/damping at Vout (small current improves ripple profile).
Tune L value / output ESR; add polymer in parallel to reduce low-freq ripple.
Refine compensation; verify phase margin around the transition region.
Route shortest high-di/dt loops; single-point AGND-DGND; keep sensitive traces away from SW.

IC hook

Choose parts with MODE, Spread-Spectrum, SYNC, and low-noise reference/EA; see Section 9.

Measurement

Scope AC-coupled, 20 MHz limit, spring ground; FFT for LF/sidebands.
Add anti-alias RC ahead of ADC if PFM unavoidable.

Layout / Parts

Mix MLCC + polymer/tantalum; add small RC/LC dampers where needed.
Keep sense/feedback traces quiet and short; proper Kelvin connections.

C) EMI (conducted / radiated)

Symptoms

Margins failing in pre-scan; interference into adjacent subsystems or cables.

Causes

Fast edges and large loop areas; input-rail resonance; unpredictable PFM spectrum.

Quick fixes

Use fixed frequency (add spread-spectrum if needed) or SYNC to a master clock.
Add π filter at VIN with damping; consider common-mode choke at egress.
Tame edges: adjust gate resistors/driver slew to reduce dV/dt and dI/dt.
Shielding/grounding: keep SW copper compact; solid GND plane; shields with thermal checks.
At connectors: CM choke + ESD/TVS; define return paths and stitching vias.

IC hook

Select ICs offering Spread-Spectrum, SYNC, and MODE control; tune SW edge options if available.

Measurement

Near-field probe + spectrum analyzer; conducted pre-scan with LISN.
Budget margin for lot/aging variance; verify across modes.

Layout / Parts

Place input ceramics tight to VIN/GND pins; minimize hot-loop length.
π filter with series R/RC damping to avoid peaking; ground stitching near edges.

Ripple, audible noise and EMI mitigation checklist for DC-DC converters — Diagnose by symptom, then apply mode, frequency, damping, and layout actions in priority order.

Decision flow:

Audible present? → apply Block A.
ADC/RF impacted? → apply Block B.
EMI margin failing? → apply Block C.

Priority: Mode (Forced-PWM / Auto-PFM + preload) → Frequency (fixed/SS/SYNC) → L/C/ESR & damping → Layout & shielding → Edge control & part swaps.

Share your waveforms/layout photos — we’ll map actions & IC replacements using this checklist. Jump to Section 9 for cross-brand picks or Submit your BOM for a 48-hour review.

Measurement & Calculations: frequency, duty, PRI↔PRF, averaging

With PWM the switching frequency is fixed, while PFM varies pulse spacing at light load. The math (PRI, PRF, duty, average) is straightforward, but measurement windows and setup differ—especially to avoid aliasing and to capture bursty behavior. Use the formula card and SOP below, then pick an IC with adjustable f_SW/SYNC/spread-spectrum.

Formula card

PRF–PRI: PRF = 1 / PRI (frequency ↔ period)
Duty cycle: D = t_on / T (T = one full period)
PWM average (logic-level): ¯V ≈ D·V_H + (1–D)·V_L (ideal 0–V_in → ¯V ≈ D·V_in)
Buck intuition (ideal CCM): V_out ≈ D·V_in (real designs deviate due to losses/comp)

Example A — PWM average

1 kHz, D=40%, 0–5 V ⇒ ¯V ≈ 0.4 × 5 = 2.0 V

Example B — PFM PRF estimate

Count 420 pulses in 10 ms ⇒ PRF ≈ 42 kHz.
Over 100 ms you may see ≈39–45 kHz due to burst spacing jitter.

Oscilloscope / DMM measurement SOP

Sampling: set ≥10× the highest frequency of interest; for PFM use a longer time window (≥5–20 ms) to compute PRF.
Trigger: for bursts, use trigger holdoff or the scope’s frequency/period counter instead of eye-balling.
Ripple method: AC-coupled, 20 MHz bandwidth limit, spring ground on the probe; measure across the output cap.
Mean & duty: use scope measurements (Mean/Duty). DMM “average” can mislead in PFM.
Avoid aliasing: match timebase to sampling rate; enable peak-detect if needed.
Where to probe: ripple at V_out; frequency at SW or gate node; verify at multiple loads.

How to pick f_SW (frequency selection)

Efficiency: lower f_SW reduces switching loss and helps light-load life (pair with Auto-PFM).
EMI/predictability: fixed frequency is easier to filter; add spread-spectrum to lower peaks; SYNC to a master clock to avoid beat notes.
Audible: avoid ~20 kHz region. Audio/RF/precision rails often use >400 kHz–2 MHz fixed frequency.
Size vs heat: higher f_SW → smaller L/C but more loss; check thermal budget.
PFM reality: if PFM must remain, keep sensitive rails above the PFM-exit current or add a small preload (see Section 3).

IC hook: In datasheets, look for Switching-frequency range, Programmable f_SW, External SYNC, Spread-Spectrum, Mode (PFM/PWM), I_q, and PFM entry/exit thresholds. Cross-brand options are summarized in Section 9; ripple/EMI fixes live in Section 4.

Share your scope screenshots — we’ll validate the setup and suggest adjustable-f_SW/SYNC/spread-spectrum regulators. Head to Section 9 or Submit your BOM for a 48-hour shortlist.

PWM Fan Control (4-Pin / 12V): standard, wiring, tach, drivers & EMI

This pattern answers: can PWM control speed, is a CPU fan PWM, how to tell 3-wire DC vs 4-pin, and what “12V PWM” means. Use the 4-pin standard for quieter, stable control and tach feedback, and apply proper drivers & EMI practices. Cross-link: levels in Section 8, noise/EMI in Section 4, IC selection in Section 9.

A) 4-Pin standard (PWM control pin, TACH feedback, 12V power)

4-pin fans separate power (+12V) and control (PWM) while exposing speed via TACH (open-collector/open-drain). Duty ratio commands RPM internally.

Pins: +12V / GND / TACH (open-drain, typically 2 pulses/rev) / PWM (logic input).
PWM frequency: ~25 kHz (outside audible; compatible with internal sampling).
Recommended drive: open-drain from MCU/FPGA with pull-up (5 V typical; check VIH/VIL in Section 8).
Tach math: RPM = (f_tach / PPR) × 60, commonly PPR = 2.

Kick-start tip: on start or very low speed, drive Duty = 100% for 200–500 ms, then drop to target duty.

B) 3-wire DC vs 4-pin: identification & compatibility

3-wire fans expose +12V / GND / TACH only—no dedicated PWM pin. Speed control is done on the power rail and can disturb tach.

Identify: check connector/keying & datasheet; confirm if a separate PWM pin exists.
3-wire control options:
- Low-side PWM chop on 12V: simple, but tach drops pulses during OFF time—sample in ON window or reshape pulses.
- Linear/constant-voltage control: quieter tach but low efficiency and higher heat.
Recommendations: prefer 4-pin for quiet/stable control; if staying 3-wire, add flyback/RC damping and calibrate tach math.

IC hooks: low-side/half-bridge drivers, hall/current sensing front-ends, robust comparators.

C) Power stage, flyback path & cable EMI

High-current fans or 3-wire PWM often need external stages. Ensure commutation currents have a low-impedance return and limit radiation.

Protection: ideal-diode/ORing for multiple sources, TVS/ESD on 12V input and cable ingress.
Drivers: low-side MOSFET or half-bridge; add Schottky/flyback path and RC snubber to tame ringing.
Cable radiation: PWM edge rate and loop area dominate; consider ferrite bead/common-mode choke at the connector, define return path.

For system EMI/noise actions, see Section 4.

D) Bring-up & speed measurement (TACH/Duty/frequency)

Check levels: PWM and TACH VIH/VIL; confirm PWM is open-drain or protected if push-pull.
Kick-start: 100% duty 200–500 ms, then step down.
Measure tach: scope TACH; compute RPM = (f_tach / PPR) × 60 (assume PPR=2 unless stated).
Curve: log Duty→RPM; define minimum stable duty and closed-loop PI gains if needed.
Noise audit: mic/SPL across duties; adjust PWM frequency/edge rate/spread-spectrum to reduce tonal peaks.

Measurement techniques (duty/average/aliasing) reference Section 5.

E) Quick reference (parameters & suggestions)

PWM freq: ~25 kHz on the control pin (4-pin standard); 3-wire low-side PWM per system trade-off.
Duty range: recommend 20–100% with startup margin.
TACH: open-drain, commonly 2 pulses/rev; add pull-up & debounce.
Levels: PWM input often 5 V logic; use level shifting if MCU is 3.3 V (see Section 8).
EMI/noise: prefer 4-pin + 25 kHz control; for 3-wire add cable filtering and edge-rate control.

IC hooks (solution building blocks)

PWM fan controller ICs (PWM in, TACH readback, stall/fault protection).
BLDC drivers (hall or sensorless) with external PWM speed command.
MOSFET/half-bridge drivers for 3-wire PWM power chopping.
Protection: TVS, ideal-diode/ORing, hot-swap/limiting as needed.

See cross-brand candidates in Section 9.

Need a quiet, closed-loop RPM BOM? Submit your BOM for a 48-hour shortlist.

PWM Dimming & Flicker (LED / Phone): high-frequency PWM, hybrid dimming, measurement & EMI

PWM dimming controls average luminance via duty cycle while keeping instantaneous LED current amplitude unchanged—great for color consistency. Risks appear when frequency is low or duty is extreme, causing visible flicker or camera banding. Use this playbook to select high-frequency PWM or hybrid dimming (PWM+Analog), and to align constant-current, layout, and EMI practices. Cross-links: frequency/duty math in Section 5, noise/EMI in Section 4, I/O levels in Section 8, driver ICs in Section 9.

A) What is PWM dimming? (incl. phone PWM)

PWM dimming varies duty cycle to set perceived brightness. Instant current amplitude stays constant, so chromaticity remains stable.

Phones / displays: many devices use PWM at low brightness; some models drop to lower PWM frequencies, which can bother sensitive users or cause rolling-band artifacts on cameras.
Alternative: DC dimming (analog current reduction) reduces flicker risk but can shift color/efficiency; a hybrid approach mixes both.
Action: raise PWM frequency and/or use hybrid dimming for eye- and camera-friendly results; see Section C below.

B) Flicker basics: visibility & comfort

Flicker perception depends on PWM frequency, modulation depth, and the observer/sensor sampling (eye or camera).

Metrics: %Flicker (modulation depth), Flicker Index—lower is better.
Comfort targets (rules of thumb): general indoor ≥ 2–3 kHz; camera/sensitive users ≥ 10–20 kHz.
Camera banding: avoid beat with shutter/frame rate; increase frequency or dither slightly (small spread) to reduce striping.

For formulas & averaging, see Section 5.

C) High-frequency PWM (>20 kHz) vs Hybrid dimming (PWM+Analog)

High-frequency PWM

Pros: near flicker-free perception; stable color; easy duty-to-luminance mapping.
Cons: higher switching loss; tougher EMI; tighter layout/filtering required.
Use when: brightness > ~20%, or where color accuracy is critical.

Actions: pick drivers supporting >20 kHz PWM; enforce compact hot loops and output damping (see Section 4).

Hybrid dimming (PWM + Analog)

Pros: cleaner ultra-low brightness, less camera banding, gentler EMI.
Cons: small color/efficiency shift at very low current; needs luminance linearization.
Use when: brightness < ~20%, camera-sensitive scenarios (phones, VR, automotive clusters).

Actions: add a small analog bias current + high-frequency PWM trim; calibrate with a log/Gamma curve.

D) Constant-current, topology, layout & EMI

Stable constant-current and tight current loops are the foundation of flicker-free, low-noise LED systems.

Topologies: LED buck / boost / buck-boost / linear CC for small power; ensure loop stability and low LED current ripple.
Sensing & routing: Kelvin sense at the shunt; keep LED+ and LED− tightly coupled; separate feedback from power switching paths.
Filters/EMI: input decoupling; small RC/LC at output to shape ripple; use spread-spectrum/SYNC if supported; avoid audible zones or mechanical resonances.

Need mitigation steps? See Section 4.

E) Measurement & evaluation (LED / Phone)

Tools: photodiode + TIA to scope (or high-speed lux/spectrometer); camera quick-check via slow-motion video.
Steps: set target brightness, record optical waveform; compute %Flicker / Flicker Index; sweep frequency/duty; test against various shutter/frame rates.
Criteria: meet project thresholds (e.g., %Flicker ≤ X%, f_PWM ≥ Y kHz).

Electrical-only probing can mislead—prefer optical for flicker judgments; math & averaging in Section 5.

F) Quick reference (targets & tips)

Recommended PWM freq: general ≥ 2–3 kHz; camera/sensitive users ≥ 10–20 kHz.
Ultra-low brightness: use hybrid dimming to keep flicker low while preserving color.
Linearity: apply log/Gamma mapping for duty→luminance calibration.
Camera-friendly: avoid beats with frame/shutter; small spread (dither) if necessary.

IC hooks (LED driver capabilities to look for)

High-frequency PWM (>20 kHz), hybrid dimming modes, wide dimming ratio (e.g., 5,000–10,000:1).
Spread-spectrum / SYNC, precise low-current regulation, built-in linearization (LUT/log mapping).
Protections (open/short/thermal), multi-string support, AEC-Q/industrial grades as needed.

See cross-brand driver picks in Section 9.

Give your target luminance and PWM frequency — we’ll return a driver shortlist and a sample-kit suggestion. Submit your BOM for a 48-hour recommendation.

Interface & Levels: VIH/VIL, idle polarity, 3.3V→12V level shifting, PWM signal basics

This section answers: What’s the max input voltage and the minimum high level (VIH/VIL)? Is PWM hardware or software? What does “Idle” mean? Is PWM AC or DC—and is it voltage or current? It also shows how to drive a 12 V load from a 3.3 V MCU safely with level shifting, isolation, and protection. Cross-links: measurements in Section 5, EMI/noise in Section 4, fan/LED applications in Section 6 & Section 7, IC picks in Section 9.

Terminology (quick answers)

VIH / VIL: input-high minimum & input-low maximum. Values depend on the input family (TTL/CMOS/Schmitt) — always use the datasheet limits (don’t assume rails).
Idle / polarity: the default line state when inactive. Define Active-High (Idle Low) or Active-Low (Idle High) so 0% duty behaves as expected.
PWM hardware vs software: prefer timer/comparator hardware outputs (low jitter). Bit-banging only for low speed / non-critical paths.
AC or DC? voltage or current? PWM is a digital voltage waveform referenced to a baseline. It controls the average power/current in the load; “current-mode PWM” usually means a constant-current driver being PWM-modulated, not a literal current square wave at the pin.

Quick myth-busters

“12V PWM” has two meanings: (a) a logic-level PWM control pin (e.g., 4-pin fan, typically 5 V max) — do not drive it with 12 V; (b) PWM chopping the 12 V power rail to the load (needs a MOSFET stage and flyback/EMI care).
VIH/VIL ≠ VDD/0: leave margin for process/temperature; confirm VIH(min)/VIL(max) in the receiver’s datasheet.
No shared ground ≠ safe: without isolation, logic domains must share ground. For safety/noise, use digital isolators/optos or isolated drivers.

3.3 V MCU → 12 V systems (what interface do you need?)

A) Logic → logic (e.g., 5 V input pin): use a level shifter / Schmitt buffer / comparator; or open-drain with a 5 V pull-up. Verify rise time and VIH/VIL.
B) Switch a 12 V load (fan/LED/coil): use a low-side N-MOSFET (or half-bridge) with proper gate drive, flyback path (for inductive loads), and an RC snubber at the SW node as needed. For high current/high f_SW, add a dedicated gate driver.
C) Isolation/noisy grounds: put a digital isolator before the gate driver (or use an isolated driver). Define the return path on the secondary side.
Measure & qualify: confirm VIH/VIL, edge rates, and dV/dt injection; run an EMI pre-scan (see Section 4).

Interface checklist

Thresholds: record VIH(min)/VIL(max) of the receiver; set idle polarity and default pulls.
Drive strength: estimate line/input capacitance; target rise/fall <10% of period; add buffer/comparator if needed.
Open-drain path: pick pull-up by rise-time target (R ≈ t_r/C_line as a first pass); validate sink current.
Protection: series resistors, clamps (TVS/Zener), reverse-polarity via ideal-diode/ORing; check surge limits.
Grounding: ensure common reference (unless isolated); single-point AGND–DGND tie for mixed-signal nodes.
Edge control: add 10–33 Ω gate/series resistors; optional small C with pull-up to soften edges (trade-off with jitter).

Quick selector (common cases)

3.3 V → 5 V logic in: open-drain + 5 V pull-up / dedicated level shifter / Schmitt buffer.
3.3 V → 12 V load (low-side): logic-level N-MOS + gate resistor + flyback diode; add driver for high current/frequency.
3.3 V → 12 V high-side: half-bridge/high-side driver (bootstrap or isolated). Verify SOA and dv/dt immunity.
Noisy/remote domain: digital isolator → local gate driver on the secondary.

3.3V MCU to 12V load: level shifting, gate driver, flyback and TVS placement — Fig 8-1 — 3.3 V MCU to 12 V load: level shifting, gate driver, flyback path & TVS (placeholder).

3.3V PWM to 5V logic input via open-drain with pull-up or level shifter comparator — Fig 8-2 — 3.3 V PWM to 5 V logic input: open-drain + pull-up, or level shifter/comparator (placeholder).

PWM idle and polarity examples: Active-High (idle low) vs Active-Low (idle high) — Fig 8-3 — PWM idle & polarity: Active-High vs Active-Low (placeholder).

IC hooks (tie-ins to Sections 6/7/9)

Level shifters / buffers / Schmitt receivers for clean logic edges on long/noisy lines.
Comparators (with hysteresis) to restore thresholds and reject noise.
Digital isolators (multi-channel PWM pass-through) for safety/ground-noise domains.
Gate drivers (low-side/high-side/half-bridge) with UVLO and TTL/CMOS-compatible inputs.

Cross-brand options listed in Section 9.

Share your interface specs (voltage, VIH/VIL, isolation needs). We’ll return level-shifting & gate-driver BOM options in 48 hours — Submit your BOM.

DC-DC Selection Basics: why DC-DC over LDO, low-Iq Auto-PFM value, cross-brand picks

This section answers why a switching DC-DC beats an LDO for efficiency/thermal, why low I_q + Auto-PFM matters for battery life, and how to shortlist cross-brand regulators with MODE/Forced-PWM, spread-spectrum and SYNC. It ties back to Section 3 (PFM & MODE) and Section 4 (ripple/EMI/noise).

A) Why DC-DC instead of an LDO?

Conclusion: when the voltage drop × load current is non-trivial, a buck converter dramatically reduces loss and temperature rise; LDOs shine only at tiny drop/low current or ultra-low-noise points.

LDO efficiency: η ≈ Vout/Vin; P_loss ≈ (Vin − Vout)·Iout; temperature rise ΔT ≈ θ_JA·P_loss.
Buck intuition: η ≈ Pout / (Pout + Psw + Pcond + I_q·Vin) (helps frame switching vs conduction vs quiescent losses).
Copyable example (12→5 V @ 0.5 A): LDO: P_loss = (12−5)·0.5 = 3.5 W; Buck (~90%): P_loss ≈ 0.28 W.
Actions: estimate (Vin−Vout)·Iout; for noise-critical rails consider buck → post-LDO.

LDO versus buck: efficiency and thermal example at 12-to-5 V, 0.5 A — LDO burns drop×current as heat; a buck shifts loss to switching/conduction, cutting thermal rise (placeholder).

B) Low I_q + Auto-PFM = standby life

Conclusion: at light load, quiescent current dominates. Auto-PFM lowers f_SW to cut switching loss and extend battery life. For audio/RF/ADC rails, Forced-PWM keeps frequency fixed at the cost of extra I_q.

Actions: define light-load current & standby budget; pick µA-class I_q parts with MODE (PFM↔PWM), plus spread-spectrum/SYNC options for EMI.
References: thresholds & transitions in Section 3; noise fixes in Section 4.

Auto-PFM effect on standby power and battery life across light-load regions — Auto-PFM reduces switching activity at light load to extend battery life (placeholder).

C) Cross-brand series to start with

TI: TPS62840 (Buck, low I_q, MODE), TPS63070 (Buck-Boost, Eco/Forced-PWM)
ST: L6981, ST1PS01 (power-save + Forced-PWM)
NXP: PCA9420 (PMIC, per-rail power-save)
Renesas: ISL91127 / ISL91126 (Buck-Boost, Auto-PFM/PWM)
onsemi: NCP1529 / NCP1521 (Buck)
Microchip: MCP1640 (Boost, auto switching)
Melexis: sensor/driver focused; pair with the above regulators

Feature mini-matrix (indicative; confirm exact values in datasheets)
Series	MODE / toggle	I_q (typ)	f_SW range	Spread-Spectrum	External SYNC	AEC-Q option
TI — TPS62840 (Buck)	MODE pin / Eco↔FPWM	µA-class	hundreds kHz–MHz class	✓ (family-dependent)	✓ (family-dependent)	varies by PN
TI — TPS63070 (Buck-Boost)	Eco / Forced-PWM selectable	low, design-dependent	hundreds kHz–MHz class	— / varies	✓ / varies	varies by PN
ST — L6981	Low-power / FPWM modes	µA-class (typical)	hundreds kHz–MHz class	✓ / varies	✓ / varies	often available
ST — ST1PS01	Power-save + FPWM	µA-class (typical)	hundreds kHz–MHz class	— / varies	— / varies	varies by PN
NXP — PCA9420 (PMIC)	Per-rail power-save/PWM via reg	low per rail (PMIC)	per rail range	— / varies	— / varies	— / varies
Renesas — ISL91127 / 91126 (Buck-Boost)	Auto-PFM/PWM + FPWM option	low, design-dependent	hundreds kHz–MHz class	— / varies	✓ / varies	varies by PN
onsemi — NCP1529 / 1521 (Buck)	Power-save / FPWM options	µA-class (typical)	hundreds kHz–MHz class	— / varies	— / varies	varies by PN
Microchip — MCP1640 (Boost)	Auto PFM/PWM (family-dep.)	low, boost-class	hundreds kHz class	— / varies	— / varies	—
Melexis — (pair with above)	—	—	—	—	—	—

Cross-brand features at a glance (placeholder visual; confirm details per datasheet).

E) Three steps to a shortlist

Mode strategy: Auto-PFM ↔ Forced-PWM (see Sec 3).
Frequency strategy: fixed frequency (+ optional spread-spectrum / external SYNC) for EMI control (see Sec 4 and Sec 5).
Filter candidates: by I_q, f_SW range, package/thermal, and AEC-Q to get 2–3 PNs for board-level validation.

Get a short-list for your load & ripple target (48h). We’ll return lead-time, pin-to-pin alternatives, compliance (AEC-Q/Industrial) and a sample-kit suggestion.

Submit your BOM

Engineer’s Checklist: datasheet must-check items before design freeze

Use this one-page checklist to review a regulator’s datasheet and avoid late rework. It distills Sec 2 (PFM vs PWM), Sec 3 (MODE/thresholds), Sec 4 (Ripple/EMI/Audible), Sec 5 (Measurements).

Parameter

Target

Measured

Notes

A) Mode & light-load behavior (PFM/PWM)

□

I_q (Typ/Max) — quiescent current (standby) [see Sec 2]

Target: __________ µA

Measured: __________ µA

Notes: ______________________

□

PFM entry/exit current thresholds & conditions [see Sec 3]

Entry: ______ mA

Exit: ______ mA

Cond: ________________________

□

MODE / Power-Save (pin logic, register bits: Eco / Forced-PWM / Auto-PFM) [see Sec 3]

Idle: High / Low

POL: AH / AL

Notes: ______________________

B) f_SW, External SYNC, Spread-Spectrum

□

Switching frequency range / programmability [see Sec 5]

Target: ______ kHz

Set: ______ kHz

Mode: Fixed / Auto

□

External SYNC capability (freq window / VIH/VIL / phase) [see Sec 4, Sec 5]

Sync: Yes / No

Range: ____–____ kHz

VIH/VIL: __________

□

Spread-Spectrum (±%, profile, on/off conditions) [see Sec 4]

± ______ %

Profile: Tri/Random

Ctrl: Pin / Reg

C) Load transient & loop stability

□

Load transient (Vout dip/overshoot, step/edge conditions) [see Sec 4]

Dip: ______ mV

Over: ______ mV

ΔI, dI/dt: __________

□

Loop margin / compensation (Phase/Gain margin) & PFM↔PWM transition stability [see Sec 3]

PM: ______ °

GM: ______ dB

Comp: Type II/III

D) Output ripple & noise (PFM vs PWM)

□

Ripple (PFM) — value & measurement conditions (AC-coupled, 20 MHz BW, probe spring) [see Sec 4, Sec 5]

Typ: ______ mVpp

Cond: __________

BW: 20 MHz

□

Ripple (PWM) — value & LC/ESR assumptions; ADC/RF alignment [see Sec 4, Sec 5]

Typ: ______ mVpp

LC/ESR: __________

Sync: Yes / No

E) EMI & clocking

□

Fixed-freq / Spread-Spectrum notes; SYNC cautions; edge-rate control options [see Sec 4]

Plan: __________

Margin: ______ dB

Edges: Slew / Rg

F) Package, thermal, current rating & compliance

□

Package & thermal (R_θJA/R_θJC), current rating, copper area guidance

Pkg: __________

R_θJA: ______

Area: __________

□

AEC-Q / Industrial certifications & differences (grade, PPAP) [see Sec 9]

Grade: ______

Status: ______

Notes: __________

Pocket card — copy/paste this block into your lab notes

■ Iq (Typ/Max): __________ µA
■ PFM entry/exit: ______ / ______ mA (cond: __________)
■ MODE / FPWM bit / PS pin: __________
■ f_SW range: ____–____ kHz | Set: ______ kHz
■ SYNC: Yes/No; Window: ____–____ kHz; VIH/VIL: __________
■ Spread-Spectrum: ± ______ % (profile: ______)
■ Transient dip/over: ______ / ______ mV (ΔI,dI/dt: ______)
■ Loop margin: PM ______ ° / GM ______ dB
■ Ripple PFM/PWM: ______ / ______ mVpp (20 MHz, AC-coupled)
■ EMI plan: Fixed / SS (±%); SYNC: Yes/No
■ Package / R_θJA / rating: __________
■ AEC-Q / Industrial: Grade ______ / PPAP ______

Need a second set of eyes? Upload your datasheet links — we’ll return a red-pen review in 48 hours. Submit your BOM.

FAQ (PFM/PWM: concepts, measurement, frequency, applications, interfaces)

Short, practical answers to the remaining FAA items. Each entry ends with a single “Further reading” link to the most relevant section in this page.

A) Concepts

How does PWM actually work?

PWM controls the average power by varying duty cycle: D = t_on/T. For an ideal 0–Vin source, average voltage ≈ D·Vin; in a buck, V_out ≈ D·V_in under steady, ideal conditions. Further reading → Section 5.

Why is PWM called PWM?

Because it modulates pulse width at a (usually) fixed period to encode the control value—unlike PFM, which varies pulse spacing. Further reading → Section 2.

How many types of PWM are there?

Common forms include edge-aligned, center-aligned (phase-correct), single/dual-edge update, complementary with dead-time, etc. Focus on frequency, duty resolution, sync, and filtering. Further reading → Section 5.

B) Math & Measurement

How to average a PWM signal?

For logic PWM with levels V_H, V_L, the average is V̄ = D·V_H + (1−D)·V_L (≈D·V_in if V_L≈0). Filtering and load shift the effective average. Further reading → Section 5.

What is the average voltage of PWM?

Ideally V̄ ≈ D·V_in; real averages depend on output impedance and any RC/LC filtering. Further reading → Section 5.

How to calculate PRF and convert PRI ↔ PRF?

PRF = 1/PRI. For PFM, count pulses over a longer window to avoid aliasing and capture burst spacing jitter. Further reading → Section 5.

How to check pulse frequency on a scope?

Use the scope’s frequency/period measurements and proper timebase; for bursty PFM add trigger holdoff and larger statistics window. Prefer AC-coupled / 20 MHz limit for ripple checks. Further reading → Section 5.

What is the PWM duty cycle?

D = t_active/T where “active” is the asserted level (Active-High or Active-Low per interface polarity/idle). Further reading → Section 8.

C) Frequency & Selection

What is the (usable) range of PWM frequency?

From hundreds of Hz to several MHz in practice. Choice balances efficiency, EMI, audible risk, and passives size. Further reading → Section 5.

How do I select PWM/switching frequency?

Avoid audible bands/beat notes; use fixed frequency (+ optional spread-spectrum or SYNC) when EMI is critical; manage low-frequency ripple in PFM. Further reading → Section 4.

D) Applications

What is PWM on a phone? Is PWM good or bad?

Many phones use PWM dimming at low brightness; low frequencies can bother sensitive users or cameras. Use higher PWM or hybrid dimming to mitigate. Further reading → Section 7.

What is PWM dimming?

It varies duty cycle to control perceived luminance while keeping instantaneous LED current constant—great for color stability; watch for flicker at low f. Further reading → Section 7.

Does PWM control fan speed? Is a CPU fan a PWM?

Yes. 4-pin CPU fans use a dedicated PWM control pin and report speed via TACH; 3-wire DC fans need power-rail PWM or linear control. Further reading → Section 6.

Can Arduino generate a PWM signal? How to make one?

Yes—via timer peripherals (e.g., analogWrite()) or libraries. Match required frequency, logic level, and drive strength; add level shifting/drivers if needed. Further reading → Section 8.

E) Interfaces & Levels

Is PWM an analog or digital signal? Is it an analog output?

It’s a digital voltage waveform whose time average can emulate an analog level after filtering or integration in the load. Further reading → Section 5.

What is PWM voltage? Is PWM voltage or current? Is it AC or DC?

PWM pins output a square voltage referenced to ground. It controls the average current/power in the load. As a signal, it’s a time-varying DC (not a symmetric AC). Further reading → Section 8.

What is the maximum input voltage for PWM? What is the minimum input high (VIH)?

Determined by the receiver’s absolute ratings and VIH/VIL thresholds—never assume it equals the supply rail; check the datasheet. Further reading → Section 8.

What is PWM idle?

The default line state when inactive. Define Active-High or Active-Low polarity so 0% and 100% duty map to the intended physical states. Further reading → Section 8.

F) Modes & Selection

What is forced PWM?

A mode that holds fixed switching frequency (no PFM) for predictable ripple/EMI and low audible noise—at the cost of higher light-load power. Further reading → Section 3.

Why use a DC-DC converter (vs LDO)?

When (V_in−V_out)·I is significant, a switching regulator slashes loss and temperature rise; add a post-LDO for ultra-clean rails. Further reading → Section 9.

How do I reduce PWM noise/ripple?

Use fixed-freq/Forced-PWM, consider spread-spectrum or SYNC, add preload if needed, optimize L/ESR/compensation, minimize loop area, and apply RC snubbers/filters where appropriate. Further reading → Section 4.

Didn’t see your question here? Ask below or Submit your BOM for a tailored answer within 48 hours.

Pulse Frequency Modulation (PFM) in DC-DC Converters — Theory, Design Trade-offs, and IC-Based Solutions

What is Pulse Frequency Modulation (PFM) in DC-DC?

Why it matters

How it works

Where you meet it

PFM vs PWM: Quick Decision Table for DC-DC Converters

PFM in Buck/Boost & MODE / Forced-PWM

Entry/Exit thresholds & transition behavior

MODE / register control (Forced-PWM)

Stability & transient control around mode switching

IC examples (cross-brand families)

Ripple / EMI / Audible Noise — Problems → Actions

A) Audible noise < 20 kHz

B) Ripple / ADC / RF integrity

C) EMI (conducted / radiated)

Measurement & Calculations: frequency, duty, PRI↔PRF, averaging

Formula card

Oscilloscope / DMM measurement SOP

How to pick fSW (frequency selection)

PWM Fan Control (4-Pin / 12V): standard, wiring, tach, drivers & EMI

A) 4-Pin standard (PWM control pin, TACH feedback, 12V power)

B) 3-wire DC vs 4-pin: identification & compatibility

C) Power stage, flyback path & cable EMI

D) Bring-up & speed measurement (TACH/Duty/frequency)

E) Quick reference (parameters & suggestions)

IC hooks (solution building blocks)

PWM Dimming & Flicker (LED / Phone): high-frequency PWM, hybrid dimming, measurement & EMI

A) What is PWM dimming? (incl. phone PWM)

B) Flicker basics: visibility & comfort

C) High-frequency PWM (>20 kHz) vs Hybrid dimming (PWM+Analog)

High-frequency PWM

Hybrid dimming (PWM + Analog)

D) Constant-current, topology, layout & EMI

E) Measurement & evaluation (LED / Phone)

F) Quick reference (targets & tips)

IC hooks (LED driver capabilities to look for)

Interface & Levels: VIH/VIL, idle polarity, 3.3V→12V level shifting, PWM signal basics

Terminology (quick answers)

Quick myth-busters

3.3 V MCU → 12 V systems (what interface do you need?)

Interface checklist

Quick selector (common cases)

IC hooks (tie-ins to Sections 6/7/9)

DC-DC Selection Basics: why DC-DC over LDO, low-Iq Auto-PFM value, cross-brand picks

A) Why DC-DC instead of an LDO?

B) Low Iq + Auto-PFM = standby life

C) Cross-brand series to start with

E) Three steps to a shortlist

Engineer’s Checklist: datasheet must-check items before design freeze

A) Mode & light-load behavior (PFM/PWM)

B) fSW, External SYNC, Spread-Spectrum

C) Load transient & loop stability

D) Output ripple & noise (PFM vs PWM)

E) EMI & clocking

F) Package, thermal, current rating & compliance

Pocket card — copy/paste this block into your lab notes

FAQ (PFM/PWM: concepts, measurement, frequency, applications, interfaces)

A) Concepts

B) Math & Measurement

C) Frequency & Selection

D) Applications

E) Interfaces & Levels

F) Modes & Selection

Submit Your BOM — 48h lead-time & alternatives

FAA → pain points

What you’ll get (48h)

IC hooks & mapping

How to pick f_SW (frequency selection)

B) Low I_q + Auto-PFM = standby life

B) f_SW, External SYNC, Spread-Spectrum