
Which ADC IC Should I Pick? (Small-Batch Selection Guide)
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Which ADC IC should I pick?
Also searched as “ADC chip / analog-to-digital converter IC”.
Start by fixing your constraints: resolution, sampling rate/bandwidth, input type/range, interface, power, and package & supply.
We recommend architectures as outcomes—SAR / ΔΣ / Pipeline / Flash—and route the details to the Types page.
Send us your specs and we’ll return 3 safe options within 48 hours, including indicative lead time and a second-source plan.
How to shortlist an ADC IC — two quick steps
Step 1 — Signal domain (bandwidth / sampling, input type & range)
≤ 200 kS/s, high precision/low noise → ΔΣ
ΔΣ trades bandwidth for higher effective resolution (ENOB) via oversampling and noise shaping—great for slow, precise measurements.
Small-batch tip: verify clean Vref/ground; even slow sensors still need anti-alias filtering.
Read more → Types1–10 MS/s, general control/DAQ, low latency → SAR
SAR balances MS/s speed, resolution, latency, and power with simple peripherals—usually the easiest to bring up.
Tip: prefer differential inputs with proper driver/RC to improve immunity and linearity.
Read more → Types> 20–40 MS/s, transients/imaging/IF sampling → Pipeline / Flash
High-speed use cases need Pipeline/Flash for throughput and front-end linearity—clock jitter and synchronization become critical.
Tip: expect LVDS/JESD204 links; plan routing and decoupling early.
Read more → TypesThresholds are practical ranges. If you’re on the border, choose by latency/synchronization first, then verify power and interface feasibility.
Input type & range — Single-ended vs Differential; mV-level vs ±V domain
Differential inputs plus a sensible full-scale range improve common-mode rejection and usable dynamic range. For mV-level signals, prioritize front-end gain and a clean reference.
Read more → Front-End & VrefStep 2 — System domain (interface, channels, package/rails/temp)
Interface: SPI (low pins, simple)
Great for 1–2 channels and moderate throughput; easy firmware. Bottlenecks appear as fs × bits × channels increases.
Read more → InterfacesInterface: LVDS (parallel diff, mid-to-high speed)
Multiple differential pairs scale bandwidth with good immunity; mind timing, skew, and length matching.
Read more → InterfacesInterface: JESD204 (high-speed serial, scalable)
Clean way to move very high data rates and keep channels in sync; clocking and link bring-up need discipline.
Read more → InterfacesThroughput quick check ≈ fs × bits × channels / efficiency (rule-of-thumb only; see Interfaces for details).
Channels: Single
Simplest layout and firmware for control and single-point measurements.
Read more → TypesChannels: Dual (may need simultaneous sampling)
For phase/compare tasks, use simultaneous-sampling or alignable apertures; multiplexed SAR can work with careful timing.
Read more → TypesChannels: Multi (synchronized)
Arrays and multi-axis work demand phase consistency; prefer synchronized architectures and links.
Read more → TypesPackage / environment / rails — QFN·SSOP·BGA, Industrial·AEC-Q, 1.8V·3.3V·5V
Package and temperature grade drive manufacturability and reliability; supply rails shape driver choices and power budget.
Read more → Supply & risk policyKey Parameters to Decide Before Shortlisting
Nominal bits rarely equal effective bits. Start from the smallest change you must resolve, convert it to %FS, and map to an ENOB target. Pick one to two bits of headroom and ensure reference noise stays well below ½ LSB(rms), otherwise resolution is wasted. Calibrate only after the front-end is quiet.
Read more → ResolutionDon’t confuse the ADC’s fs with signal bandwidth. Budget a Nyquist guard (typically 20–30%) and set the anti-alias filter so out-of-band energy doesn’t fold back. Slow sensors still alias when switching noise leaks in. Decide by usable bandwidth, not a marketing max-rate.
Read more → Anti-aliasSingle-ended is simple; differential buys common-mode rejection and dynamic range. Choose full-scale range so codes are used efficiently. mV-level inputs usually need gain and a low-impedance driver; high source impedance calls for buffering. Match FSR and Vref to the real signal.
Read more → Front-End & VrefQuick check: throughput ≈ fs × bits × channels / efficiency. SPI is easy but hits limits early; LVDS adds lanes and immunity; JESD204 scales cleanly at very high rates with stricter clocking. Confirm framing overhead and firmware/FPGA resources before locking in.
Read more → InterfacesControl loops, protection trips, and synchronized arrays care about group delay. SAR is low-latency; delta-sigma adds filtering delay; pipeline/flash can add cycles. Decide by loop stability and channel-alignment needs, then shortlist devices within that architecture class.
Read more → TypesSNR reflects random noise; THD and SFDR expose harmonic distortion and spurs. Read datasheet FFT footnotes (input level, bandwidth, averaging) to avoid apples-to-oranges. If spectral purity matters, prioritize SFDR; for precision DC, focus on low noise density and ENOB.
Read more → ResolutionPower scales with speed and channels. Rails set driver choices, input-range handling, and sequencing; leave thermal margin for hot environments. For battery or tight thermal budgets, compare energy-per-sample, not just “typical power” lines.
Read more → Front-End & VrefQFN is assembly-friendly and compact; BGA helps pin-count and signal integrity but complicates rework. Confirm stencil, paste, and reflow constraints, and choose the right temperature grade (Industrial or AEC-Q). Prefer families with footprint-compatible options.
Read more → IC selection policyScreen NRND/EOL and lifecycle stability early, and line up second-source candidates. Ask for indicative lead-time windows and MOQ/Cut-Tape options. Favor pin-compatible families and plan a swap test (timing, noise, codes) before committing a layout.
Read more → Supply strategyAperture/clock jitter converts to SNR loss proportional to input frequency—harmless at low kHz, severe at MHz. Set a jitter budget from required SNR, isolate clocks from noisy loads, and keep references clean and well-decoupled.
Read more → Anti-aliasFind Your Path by Scenario
Low-bandwidth sensing benefits from higher effective resolution and a quiet reference. Keep full-scale range close to the signal and budget an anti-alias RC even at low rates.
General DAQ and power/current monitoring favor SAR for low latency and easy bring-up. Size the driver and anti-alias filter so the source sees a stable load at the sampling instant.
High-throughput work needs Pipeline/Flash and a link that carries the data while keeping channels synchronized. Clock quality and lane timing dominate final performance.
Audio chains typically use audio-grade delta-sigma with I²S/TDM framing and well-managed references and clocks. This page doesn’t expand details—see the types overview.
Use isolated front-ends and differential inputs with isolated power and careful return paths. Validate CMTI and creepage/clearance early to avoid late-stage redesigns.
What you’ll receive (48h)
- Primary (balanced performance/risk)
- Conservative (robust & production-friendly)
- Value (cost & replaceability)
Not a precise quote; shows week/month windows, trend, and risk drivers.
- Pin/function & package compatibility
- Driver/interface (SPI/LVDS/JESD204) alignment
- Form/fit/function risk notes
- RC anti-alias near 0.3–0.4×fs; short loop, local ground
- 10–100 Ω series before S/H when needed
- Vref decoupling 10 µF ∥ 0.1 µF at the pin
- Clean LDO/reference; avoid noisy digital rails
Representative vendors (examples only)
We remain brand-neutral and avoid long SKU lists; exact parts are selected per your constraints and risk posture.
Why we don’t publish long part lists
- Supply, packages, and silicon revisions change fast; public lists stale quickly.
- We prioritize risk coverage & compatible alternates, not catalog volume.
- Each proposal includes drop-in or near-drop-in alternates where practical.
Send your constraints — get 3 safe options in 48 hours
Keep it engineering-focused. Required fields marked with *.
Related Reading
Architecture sets speed, latency, and noise behavior. Pick a direction before shortlisting parts.
Read more →Nameplate bits aren’t equal to effective bits. Relate ENOB and SNR to your accuracy target.
Read more →Stop out-of-band energy from folding into baseband. Even low-speed sensors need the right filter.
Read more →Make sure your link can move the data: throughput ≈ fs × bits × channels / efficiency.
Read more →When the internal converter isn’t enough—consider noise, bandwidth, latency, and isolation.
Read more →Understand what specs mean in practice and how to catch problems during bring-up.
Read more →